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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
256KB and 512KB BurstRAMTM Secondary Cache Modules for PowerPCTM PReP/CHRP Platforms
The MPC2104/5/6/7 are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchronous data RAMs. The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola's 5 V 32K x 18; the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the 5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst capability is provided in that two burst addresses bypass the address latch. Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in-depth description of the cache module. This EEPROM will be available on future revisions of the module family. The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected. All of these cache modules are plug and pin compatible with each other. * * * * * * * * * * * * * PowerPC-style Burst Counter on Chip (MPC2104/5/6) Flow-Through Data I/O (MPC2104/5/6) Plug and Pin Compatibility of entire Module Family Multiple Clock Pins for Reduced Loading All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6) Three State Outputs Byte Write Capability Fast Module Clock Rates: Up to 66 MHz Fast SRAM Access Times: 10 ns for Tag RAM Match 9 ns for Data RAM (MPC2104/5/6) 15 ns for Data RAM (MPC2107) Decoupling Capacitors for Each Fast Static RAM High Quality Multi-Layer FR4 PWB With Separate Power and Ground Planes 182 Pin Card Edge Module Burndy Connector, Part Number: ELF182JSC-3Z50
MPC2104 MPC2105 MPC2106 MPC2107
BurstRAM is a trademark of Motorola. PowerPC is a trademark of International Business Machines Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice. 11/8/95
(c) Motorola, Inc. 1995 MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 1
PIN ASSIGNMENT 182-LEAD DIMM TOP VIEW - CASE TBD
VSS PD1/IDSDATA PD3 DH31 DH29 DH27 DH25 VCC3 CWE3 DH23 DH21 DH18 VSS DH16 CWE2 DH14 DH13 VCC5 DH10 DH8 CWE1 DH6 VCC3 DH4 VSS CLK0 VSS DH1 CWE0 DL31 DL30 VSS DL29 DL27 DL25 VCC5 CWE7 DL23 DL21 DL19 VSS DL17 CWE6 DL15 DL13 VSS DL10 DL8 CWE5 DL6 VCC3 DL5 DL2 VSS CLK3 VSS CLK4 VSS CWE4 ALE VCC3 ADDR1 RESERVED CNTEN0 CNTEN1 VCC5 VCC5 A27 A24 A22 A20 VSS A18 A16 A15 A14 VCC3 A10 A8 A6 VSS A4 A2 A1 BURSTMODE VCC5 VALIDIN TWE STANDBY DIRTYOUT VSS
92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91
VSS PD0/IDSCLK PD2 DH30 DH28 DH26 DH24 VCC3 DP3 DH22 DH20 DH19 VSS DH17 DP2 DH15 DH12 VCC5 DH11 DH9 DP1 DH7 VCC3 DH5 DH3 DH2 DH0 DP0 VSS CLK1 VSS DL28 DL26 DL24 DP7 VCC5 DL22 DL20 DL18 DL16 VSS DP6 DL14 DL12 DL11 VSS DL9 DP5 DL7 DL4 VCC3 DL3 DL1 DL0 VSS CLK2 VSS DP4 COE0 COE1 VCC3 ADDR0 RESERVED ADS0 ADS1 VCC5 VCC5 A28 A26 A25 A23 VSS A21 A19 A17 A13 VCC3 A12 A11 A9 VSS A7 A5 A3 A0 VCC5 TCLR MATCH TOE DIRTYIN VSS
NOTES: 1. VCC5 and VCC3 must be connected on all modules.
MPC2104*MPC2105*MPC2106*MPC2107 2
MOTOROLA FAST SRAM
MPC2104/MPC2105 BLOCK DIAGRAM
A28 A27 A14 - A26 A13 ADS0 CNTEN0 COE0 STANDBY VCC5 via 100 '244 A0 A1 A2 - A14 A15 TSC BAA G E TSP A0 A1 A2 - A14 A15 TSC BAA G E TSP A0 MCM67Mx18 K DQ0 - DQ8 DQ9 - DQ17 LW UW CLK1 DL0 - DL7 + DP4 DL8 - DL15 + DP5 CWE4 CWE5 MCM67Mx18 K DQ0 - DQ8 DQ9 - DQ17 LW UW CLK0 DH16 - DH23 + DP2 DH24 - DH31 + DP3 CWE2 CWE3 PD0/IDSCLK J2 J3 A1 A2 - A14 A15 TSC BAA G E TSP A0 MCM67Mx18 K DQ0 - DQ8 DQ9 - DQ17 LW UW CLK1 DL16 - DL23 + DP6 DL24 - DL31 + DP7 CWE6 CWE7 256KB J5 J4 J3 J2 J1 J0 no stuff 0 0 0 0 no stuff VSS VCC5 via 100 MATCH DIRTYOUT VCC3 NC NC 512KB 0 0 0 no stuff no stuff 0 EEPROM 256KB no stuff no stuff no stuff no stuff 0 no stuff EEPROM 512KB 0 no stuff no stuff no stuff no stuff 0 PD1/IDSDATA X24C00 (OPTIONAL) SCL SDA MCM67Mx18 K DQ0 - DQ8 DQ9 - DQ17 LW UW CLK0 DH0 - DH7 + DP0 DH8 - DH15 + DP1 CWE0 CWE1 CLK3 CLK4 ALE ADS1 CNTEN1 COE1 ADDR0 ADDR1 PD2 PD3 = NC = NC = NC = NC = NC = NC = NC = NC = NC J4
A1 A2 - A14 A15 TSC BAA G E TSP
J1 J0 A14 - A26 A2 - A12 A1 TCLR TWE CLK2 VALIDIN DIRTYIN TOE
TAG: 16K x 12 + V + D A13 A0 - A12 TDQ0 - TDQ10 TDQ11 RESET SW TW K VALIDD DIRTYD TG TT1, WTD, E1 SFUNC, SG TAG, TAD, E2 TAH, PWRDN MATCH DIRTYQ VCCQ VALIDQ WTQ
J5
Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs.
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 3
MPC2106 BLOCK DIAGRAM
64K X 18 BURST A0 - A15 K TSC DQ0 - DQ8 BAA DQ9 - DQ17 G LW E PAL 64K X 18 BURST PA12L K A0 - A15 TSC DQ0 - DQ8 DQ9 - DQ17 BAA LW G E UW 64K X 18 BURST A0 - A15 K TSC DQ0 - DQ8 BAA DQ9 - DQ17 G LW E UW 64K X 18 BURST A0 - A15 TSC BAA G E K DQ0 - DQ8 DQ9 - DQ17 LW UW CLK1 DH16 - DH23 + DP2 DH24 - DH31 + DP3 CWE2 CWE3 A13 - A26 14 A0 - A11 TCLR CLK3 DL0 - DL7 + DP4 TWE DL8 - DL15 + DP5 CLK2 CWE4 VALIDIN CWE5 DIRTYIN TOE CLK4 DL16 - DL23 + DP6 DL24 - DL31 + DP7 CWE6 CWE7 A13 - A26 A0 - A11 TCLR CLK0 DH0 - DH7 + DP0 TWE DH8 - DH15 + DP1 CLK2 CWE0 VALIDIN CWE1 DIRTYIN TOE CLK1 DH16 - DH23 + DP2 DH24 - DH31 + DP3 CWE2 CWE3 ALE ADDR0 ADDR1 PD2 PD3 = NC = NC = NC = NC J1 UW
A13 - A28 ADS0 CNTEN0 COE0 A12 STANDBY
'244
PA12
CLK0 DH0 - DH7 + DP0 DH8 - DH15 + DP1 CWE0 CWE1
PD0/IDSCLK J0
PD1/IDSDATA
X24C00 (OPTIONAL) SCL SDA
TAG: 16K x 12 + V + D TT1, WTD A0 - A13 TDQ0 - TDQ11 SFUNC, SG TAH, TAG, TAD RESET PWRDN SW MATCH TW DIRTYQ K VALIDD VCCQ DIRTYD TA, VALIDQ TG WTQ E1 E2 VSS VCC5 via 100 MATCH DIRTYOUT VCC3 NC NC A12 VDD
TAG: 16K x 12 + V + D A0 - A13 TT1, WTD TDQ0 - TDQ11 SFUNC, SG RESET TAH, TAG, TAD PWRDN SW MATCH TW DIRTYQ K VALIDD VCCQ DIRTYD TA, VALIDQ TG WTQ E1 E2 VSS VCC5 via 100 MATCH DIRTYOUT VCC3 NC NC VSS A12
64K X 18 BURST ADS1 CNTEN1 COE1 K A0 - A15 DQ0 - DQ8 TSC DQ9 - DQ17 BAA LW G UW E 64K X 18 BURST A0 - A15 K TSC DQ0 - DQ8 BAA DQ9 - DQ17 G LW E UW 64K X 18 BURST A0 - A15 K TSC DQ0 - DQ8 BAA DQ9 - DQ17 G LW E UW 64K X 18 BURST A0 - A15 TSC BAA G E K DQ0 - DQ8 DQ9 - DQ17 LW UW
CLK3 DL0 - DL7 + DP4 DL8 - DL15 + DP5 CWE4 CWE5
CLK4 DL16 - DL23 + DP6 DL24 - DL31 + DP7 CWE6 CWE7
J1 J0
1M 0 0
EEPROM 1M no stuff no stuff
Note: All 64K X 18 TSP signals are tied to VCC via a 100 resistor. Edge connector A28 connects to the 64K x 18 A0; edge connector A27 connects to the 64K x 18 A1.
MPC2104*MPC2105*MPC2106*MPC2107 4
MOTOROLA FAST SRAM
MPC2107 BLOCK DIAGRAM
ADDR0 ADDR1 A14 - A26 ALE COE0 STANDBY '373 A0 A1 MCM6206
A2 - A14 G E A0 A1 DQ0 - DQ7 W DH0 - DH7 CWE0 PD0/IDSCLK MCM6206 J2 J3 PD1/IDSDATA X24C00 (OPTIONAL) SCL SDA
A2 - A14 G E A0 A1 DQ0 - DQ7 W
DH8 - DH15 CWE1
MCM6206
A2 - A14 G E A0 A1 DQ0 - DQ7 W
DH16 - DH23 CWE2
MCM6206
VSS A14 - A26 13 A2 - A13 DH24 - DH31 CWE3 TCLR TWE CLK2 VALIDIN DIRTYIN TOE DL0 - DL7 CWE4
A2 - A14 G E A0 A1 DQ0 - DQ7 W
MCM6206
TAG: 16K x 12 + V + D A13 A0 - A12 TT1, WTD, E1 TDQ0 - TDQ11 SFUNC, SG RESET TAH, TAG, TAD E2, PWRDN SW MATCH TW DIRTYQ K VALIDD VCCQ DIRTYD TA, VALIDQ TG WTQ
VSS VCC5 via 100 MATCH DIRTYOUT VCC3 NC NC
A2 - A14 COE1 G E A0 A1 DQ0 - DQ7 W
MCM6206
A2 - A14 G E A0 A1 DQ0 - DQ7 W
DL8 - DL15 CWE5
MCM6206
CLK0, 1, 3, 4 ADS0, ADS1 CNTEN0, CNTEN1 A27, A28 DP0 - DP7 BURSTMODE PD2 PD3
= NC = NC = NC = NC = NC = NC = NC J1
A2 - A14 G E A0 A1 DQ0 - DQ7 W
DL16 - DL23 CWE6 256KB 0 0 0 EEPROM 256KB no stuff no stuff no stuff
MCM6206
J3 J2 J1 DL24 - DL31 CWE7
A2 - A14 G E DQ0 - DQ7 W
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 5
PIN DESCRIPTIONS
Pin Locations 68, 69, 70, 71, 73, 74, 75, 76, 78, 79, 80, 82, 83, 84, 85, 159, 160, 161, 162, 164, 165, 166, 167, 169, 170, 171, 173, 174, 175 62 153 30, 56, 117, 146, 148 Symbol A0 - A28 Type Input Description Address Inputs - (MSB:0, LSB:28)
ADDR0 ADDR1 CLK0 - CLK4
Input Input Input
Least significant address bit when asynchronous Data RAMs are used. Next to least significant address bit when asynchronous Data RAMs are used. Clock Inputs - CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only. For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0-CLK2 only. For MPC2107 use CLK2 only. High Data Bus - (MSB:0, LSB:31)
4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 27, 95, 96, 97, 98, 101, 102, 103, 105, 107, 108, 110, 111, 113, 115, 119 32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 121, 122, 124, 125, 126, 129, 130, 131, 133, 135, 136, 138, 139, 141, 143, 144 9, 15, 21, 28, 35, 42, 48, 58 3, 94 2 93 64, 65 151 155, 156 59, 60 100, 106, 112, 120, 128, 134, 140, 150 87 88 178 179 89 90 181 180 176, 63, 154 8, 23, 51, 61, 77, 99, 114, 142, 152, 168 18, 36, 66, 67, 86, 109, 127, 157, 158, 177 1, 13, 29, 31, 41, 46, 55, 57, 72, 81, 91, 92, 104, 116, 118, 123, 132, 137, 145, 147, 149, 163, 172, 182 176
DH0 - DH31
I/O
DL0 - DL31
I/O
Low Data Bus - (MSB:0, LSB:31)
DP0 - DP7 PD2, PD3 PD0/IDSCLK PD1/IDSDATA ADS0, ADS1 ALE CNTEN0, CNTEN1 COE0, COE1 CWE0 - CWE7 TCLR MATCH VALIDIN TWE TOE DIRTYIN DIRTYOUT STANDBY RESERVED VCC3 VCC5 VSS
I/O Output Input I/O Input Input Input Input Input Input Output Input Input Input Input Output Input
Data Parity Bits - (MSB:0, LSB:7) Presence detect bits. Presence detect bit 0/EEPROM serial clock. (EEPROM option only.) Presence detect bit 1/EEPROM serial data. (EEPROM option only.) Data RAM Address Strobe - For MPC2104 or MPC2105 use ADS0 only. For MPC2106 use ADS0, ADS1. Data RAM Address Latch Enable - Use for asynchronous Data RAM only. Data RAM Count Enables - For MPC2104 or MPC2105 use CNTEN0 only. For MPC2106 use CNTEN0, CNTEN1. Data RAM Output Enables - For MPC2104 or MPC2105 use COE0 only. For all others use COE0, COE1. Data RAM Write Enables - (MSB:0, LSB:7) Tag RAM clear. Tag RAM active high match indication. Tag RAM valid bit. Tag RAM write enable. Tag RAM output enable. Dirty input bit. Dirty output bit. Standby pin. Reduces standby power consumption. Reserved pin.
Input Input Input
+ 3.3 V power supply. Must be connected. + 5 V power supply. Must be connected. Ground
BURSTMODE
Input
Burstmode. 0 = Linear, 1 = Interleaved.
MPC2104*MPC2105*MPC2106*MPC2107 6
MOTOROLA FAST SRAM
DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY H L L X X X X ADS0 L L L H H H H CNTEN0 X X X L L H H CWEx X L H L H L H CLKx L-H L-H L-H L-H L-H L-H L-H Address Used N/A External Address External Address Next Address Next Address Current Address Current Address Operation Deselected Write Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst
NOTES: 1. X means Don't Care. 2. All inputs except COE must meet set-up and hold times for the low-to-high transition of clock (CLK0 - CLK4). 3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation Read Read Write Deselected COE L H X X I/O Status Data Out (DQ0 - DQ8) High-Z High-Z -- Data In High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, COE must be high before the input data required set-up time and held high through the input data hold time.
DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
STANDBY H L L L COE0, COE1 X H L X CWE0 - CWE7 X H H L Operation Deselected Output Disabled Read Write I/O Status High-Z High-Z Data Out High-Z
NOTES: 1. X means Don't Care. 2. For a write operation following a read operation, COE0, and COE1 must be high before the input data required set-up time, and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating Power Supply Voltage Voltage Relative to VSS Output Current (per I/O) Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature Data RAM Tag Symbol VCC Vin, Vout Iout PD Tbias TA Value - 0.5 to + 7.0 - 0.5 to VCC + 0.5 30 20 8.1 - 10 to + 85 0 to +70 Unit V V mA W C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 7
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Symbol VCC VIH VIL Min 4.75 2.2 - 0.5* Max 5.25 VCC + 0.3** 0.8 Unit V V V
* VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width 20 ns) for I 20.0 mA. ** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.
DC CHARACTERISTICS
Parameter Input Leakage Current (All Inputs, Vin = 0 to VCC) Output Leakage Current (COE = VIH, Vout = 0 to VCC) TTL Output Low Voltage (IOL = + 8.0 mA) TTL Output High Voltage (IOH = - 4.0 mA) Data RAM Tag Data RAM Tag Symbol Ilkg(I) Ilkg(O) VOL VOH Min -- -- -- 2.4 Max 1.0 5.0 1.0 5.0 0.4 -- Unit A A V V
POWER SUPPLY CURRENTS
Parameter AC Supply Current (COE = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time 20 ns) MPC2104 MPC2105 MPC2106 MPC2107 ISB1 MPC2104 MPC2105 MPC2106 MPC2107 620 700 1400 960 Symbol ICCA 1480 1420 2840 1400 mA Max Unit mA
AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH, VIL = 0.0 V and VIH 3.0 V, Cycle Time 20 ns)
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance (A13 - A28) (Data RAM Control Pins) (CLK0 - CLK4) (Tag Control Pins) (MATCH, DIRTYOUT) (DH0 - DH31, DL0 - DL31) (A0 - A11) Symbol Cin Typ -- 16 8 -- -- 6 -- Max 15 20 10 5 7 8 7 Unit pF
Tag Output Capacitance Data RAM Input/Output Capacitance Tag Input/Output Capacitance
Cout CI/O CI/O
pF pF pF
MPC2104*MPC2105*MPC2106*MPC2107 8
MOTOROLA FAST SRAM
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5% TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 7)
MPC2104 MPC2105 MPC2106 Parameter Cycle Time Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Clock High Pulse Width Clock Low Pulse Width Setup Time Setup Times: Address Address Status Data In Write Address Advance Chip Enable Address Address Status Data In Write Address Advance Chip Enable Symbol tKHKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tKHKL tKLKH tAVKH tSVKH tDVKH tWVKH tBAVVKH tEVKH tKHAX tKHTSX tKHDX tKHWX tKHBAX tKHEX Min 15 -- -- 6 3 0 2 -- 5 5 7.5 2.5 Max -- 9 5 -- -- -- 6 6 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 5, 6 5 4 Notes
Hold Times:
0.5
--
ns
5
NOTES: 1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW. 2. All read and write cycle timings are referenced from CLK or COE. 3. COE is a don't care when UW or LW is sampled low. 4. Maximum access times are guaranteed for all possible PowerPC external bus cycles. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled. 6. 5 ns of set-up delay is incurred in address buffers. 7. Applies to MPC2104, MPC2105, and MPC2106.
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 9
SYNCHRONOUS DATA RAM READ CYCLE
tKHKH CLK1, CLK0 tKLKH tKHKL
ADS0 tTSVKH tAVKH A(12, 13, 14 - 26) (See Note 1) A1 tKHAX A2 tKHTSX
CWE0 - CWE7 tWVKH tEVKH STANDBY tKHEX tKHWX
tBAVKH CNTEN0 tKHQV tGLQV COE tGLQX tKHQX1 DATA OUT Q (A1) tGHQZ tKHQX2 Q (A2)
tKHBAX
tKHQV
tKHQZ
Q (A2 + 1)
Q (A2 + 2)
Q (A2 + 3)
READ
BURST READ
NOTES: 1. Cache addresses used are: 14 - 26 for MPC2104 and MPC2107; 13 - 26 for MPC2105; and 12 - 26 for MPC2106. 2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with A2 as the base address.
MPC2104*MPC2105*MPC2106*MPC2107 10
MOTOROLA FAST SRAM
SYNCHRONOUS DATA RAM WRITE CYCLE
tKHKH CLK1, CLK0 tKLKH tKHKL tSVKH ADS0 tKHTSX
tAVKH A(12, 13, 14 - 26) A1
tKHAX
tAVKH A2
tKHAX
tWVKH CWE0 - CWE7
tKHWX
tEVKH STANDBY
tKHEX
tBAVKH CNTEN0
tKHBAX
tDVKH DATA IN D (A1) D (A2)
tKHDX D (A2 + 1) D (A2 + 2) D (A2 + 3)
SINGLE WRITE
BURST WRITE
NOTES: 1. Cache addresses used are: 14 - 26 for MPC2104 and MPC2107; 13 - 26 for MPC2105; and 12 - 26 for MPC2106. 2. COE0 = VIH
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 11
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5% TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
ASYNCHRONOUS DATA RAMs READ CYCLE TIMING (See Notes 1 and 8)
MPC2107-15 Parameter Cycle Time Address Access Time Enable Access Time Output Enable Access Time Output Hold from Address Change Enable Low to Output Active Enable High to Output High-Z Output Enable Low to Output Active Output Enable High to Output High-Z Power Up Time Symbol tAVAV tAVQV tELQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH Min 15 -- -- -- 4 4 0 0 0 0 Max -- 15 15 8 -- -- 8 -- 7 -- Unit ns ns ns ns ns ns ns ns ns ns 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 3 Notes 2
Power Down Time tEHICCL -- 15 ns NOTES: 1. W is high for read cycle. 2. All timings are referenced from the last valid address to the first transitioning address. 3. Addresses valid prior to or coincident with E going low. 4. At any given voltage and temperature, tEHQZ(max) is less than tELQX(min), and tGHQZ(max) is less than tGLQX(min), both for a given device and from device to device. 5. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 6. This parameter is sampled and not 100% tested. 7. Device is continuously selected (E = VIL, COE0 = VIL). 8. Applies to MPC2107.
MPC2104*MPC2105*MPC2106*MPC2107 12
MOTOROLA FAST SRAM
ASYNCHRONOUS READ CYCLE 1 (See Note 7)
tAVAV A (ADDRESS) tAXQX Q (DATA OUT) PREVIOUS DATA VALID tAVQV DATA VALID
ASYNCHRONOUS READ CYCLE 2 (See Note 3)
tAVAV A (ADDRESS) tAVQV tELQV E (CHIP ENABLE) tELQX G (OUTPUT ENABLE) tGLQV tGLQX Q (DATA OUT) HIGH-Z tELICCH VCC SUPPLY CURRENT DATA VALID tEHICCL HIGH-Z tGHQZ tEHQZ
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 13
ASYNCHRONOUS DATA RAMs WRITE CYCLE 1 (See Notes 1 and 2)
MPC2107-15 Parameter Write Cycle Time Address Set-up Time Address Valid to End of Write Write Pulse Width Write Pulse Width, G High Data Valid to End of Write Data Hold Time Write Low to Output High-Z Write High to Output Active Write Recovery Time Symbol tAVAV tAVWL tAVWH tWLWH tWLEH tWLWH tWLEH tDVWH tWHDX tWLQZ tWHQX tWHAX Min 15 0 12 12 10 7 0 0 5 0 Max -- -- -- -- -- -- -- 7 -- -- Unit ns ns ns ns ns ns ns ns ns ns 5,6,7 5,6,7 4 Notes 3
NOTES: 1. A write occurs during the overlap of E low and W low. 2. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E VIH, the output will remain in a high impedance state. 5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device. 6. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. 7. This parameter is sampled and not 100% tested.
ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV A (ADDRESS) tAVWH E (CHIP ENABLE) tWLEH tWLWH W (WRITE ENABLE) tAVWL D (DATA IN) tWLQZ Q (DATA OUT) HIGH-Z HIGH-Z tWHQX tDVWH DATA VALID tWHDX tWHAX
MPC2104*MPC2105*MPC2106*MPC2107 14
MOTOROLA FAST SRAM
ASYNCHRONOUS DATA RAMs WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MPC2107-15 Parameter Write Cycle Time Address Setup Time Address Valid to End of Write Enable to End of Write Data Valid to End of Write Data Hold Time Write Recovery Time Symbol tAVAV tAVEL tAVEH tELEH tELWH tDVEH tEHDX tEHAX Min 15 0 12 10 7 0 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 3, 4 Notes 0
NOTES: 1. A write occurs during the overlap of E low and W low. 2. All timings are referenced from the last valid address to the first transitioning address. 3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.
ASYNCHRONOUS WRITE CYCLE 2 (E Controlled, See Note 1)
tAVAV A (ADDRESS) tAVEH E (CHIP ENABLE) tAVEL tWLEH W (WRITE ENABLE) tDVEH D (DATA IN) DATA VALID tEHDX tELEH tELWH tEHAX
Q (DATA OUT)
HIGH-Z
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 15
TAG RAM
RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)
TCLR L L CLK L-H L-H TWE H L TAG High-Z -- VLDout L(3) -- DTYout L(3) -- WTout L(3) -- MATCH L(3) -- TA High-Z -- Operation Reset Status Not Allowed POWER Active --
NOTES: 1. H = VIH, L = VIL, X = don`t care, -- = unrelated. 2. TOE is X for this table.
READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)
TOE L H TWE H X CLK X X TAG DOUT High-Z VLDin -- -- DTYin -- -- WTin -- -- VLDout -- -- DTYout -- -- WTout -- -- MATCH DOUT -- Operation Read Tag I/O Tag I/O Disable
WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)
TOE H L TWE L L CLK L-H L-H TAG DIN -- VLDin -- -- DTYin -- -- WTin -- -- VLDout DOUT -- DTYout DOUT -- WTout DOUT -- MATCH L -- Operation Write Tag I/O Not Allowed
NOTES: 1. H = VIH, L = VIL, X = don`t care, -- = unrelated. 2. This table applies when RESET and PWRDN are high. 3. DOUT in this case is the same as DIN. The input data is written through to the outputs during the write operation.
MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)
TOE X L H H TWE X H L H TAG -- DOUT DIN TAGIN VLD(4) -- -- DIN L DTY(4) -- -- DIN -- WT(4) -- -- DIN -- MATCH DOUT L L L Operation Selected Read Tag I/O Write Tag I/O, Status Bits Invalid Data - Dedicated Status Bits
H H TAGIN H -- -- M Match - Dedicated Status Bits NOTES: 1. H = VIH, L = VIL, X = don`t care, -- = unrelated. 2. M = high if TAGIN equals the memory contents at the address; M = low if TAGIN does not equal the ocntents at that address. 3. PWRDN and RESET are high for this table. OES and CLK are X. 4. This column represents the stored memory cell data for the given status bit at the selected address.
MPC2104*MPC2105*MPC2106*MPC2107 16
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM Parameter Clock Access Time Output Enable to Output Valid Output Enable to Output Active Output Disable to Q High-Z Status Bit Hold from Address Change Address Access Time Status Bits Tag Bit Hold from Address Change Address Access Time Tag Bits Symbol tKHQV tGLQV tGLQX tGHQZ tAXSX tAVSV tAVQX tAVQV Min -- -- 0 1 3 -- 3 -- Max 10 8 -- 6 -- 10 -- 12 Unit ns ns ns ns ns ns ns ns Notes
NOTES: 1. Set-up and hold times, W (write) referes to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM Parameter Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock High to Output Active Symbol tKHKH tKHKL tKLKH tKHQX Min 15 4.5 4.5 1.5 Max -- -- -- -- Unit ns ns ns ns Notes
Set-up Times Hold Times
Status Output Hold Clock High to Status Bits Valid
Address Write Address Write
tAVKH tWVKH tKHAX tKHWX tKHSX tKHSV
3 1.5
0 --
-- --
-- 9
ns ns
ns ns
NOTES: 1. Set-up and hold times, W (write) referes to TWE. 2. A read cycle is defined by TWE high. A write cycle is defined by TWE low. 3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles. 4. Tag writes are synchronous.
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 17
TAG RAM WRITE AND READ CYCLES (See Note 2)
STATUS WRITE TAG WRITE TAG READ AFTER WRITE TAG READ AFTER READ
CLK t KLKH t KHKH
t KHKL
A(12, 13, 14-26) (See Note 3) VALID t KHAX t WVKH t KHWX VALID
VALID t AVQV t AXQX
t AVKH
MPC2104*MPC2105*MPC2106*MPC2107 18
t KHWX t KHQV (See Note 1) t KHQX (See Note 1) t GHQZ t GLQV t GLQX t KHAX VALID INPUT t AVSV t KHWX VALID t KHSV t KHSX VALID VALID VALID VALID t AXSX VALID OUTPUT VALID OUTPUT VALID OUTPUT t AVSV t AXSX
TWE
t WVKH
TOE
t AVKH
A0 - A11
t WVKH
VALIDIN DIRTYIN
DIRTYOUT
MOTOROLA FAST SRAM
NOTE: 1. Transition is measured plus or minus 200 mV from steady state. 2. TCLR = High. 3. Cache addresses used are: 14-26 for MPC2004 and MPC2007; 13-26 for MPC2005; 12-26 for MPC2006 and MPC2009.
TAG RAM MATCH CYCLE
Tag RAM Parameter Clock High Write to MATCH Invalid Clock High Read to MATCH Valid Address Valid to MATCH Valid MATCH Valid Hold from Address Change TOE Low to MATCH Invalid TOE High to MATCH Valid Symbol tKHML tKHMV tAVMV tAXMX tGLML tGHMX Min -- -- -- 2 -- -- Max 7 10 10 -- 7 8 Unit ns ns ns ns ns ns Notes
TAG RAM RESET (TCLR) CYCLE
Tag RAM Parameter TCLR Set-up Time TCLR Hold Time Status Bit Reset Time Status Bit Hold from TCLR Low TCLR Low to MATCH Invalid TCLR High to MATCH Valid TCLR Low to TAG High-Z TCLR High to TAG Active STANDBY Set-up to TCLR Low TCLR High to TWE Low Symbol tSTC tHTC tSRST tSHRS tRSML tRSMV tRSQZ tRSQX tPDSR tRHWX Min 4 1 -- 2 -- -- -- -- 30 80 Max -- -- 60 -- 10 100 10 100 -- -- Unit ns ns ns ns ns ns ns ns ns ns Notes
AC TEST LOADS
+5 V Z0 = 50 OUTPUT 50 VL = 1.5 V OUTPUT 255 5 pF 480
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1A
Figure 1B
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 19
TAG RAM MATCH CYCLE
CLK
MPC2104*MPC2105*MPC2106*MPC2107 20
VALID ADDRESS VALID MATCH DATA FROM: PROCESSOR t WVKH t KHWX t KHWX t WVKH t WVKH TAG RAM PROCESSOR t GLML t KHML MATCH VALID t KHMV VALID VALID t GLMX
A(12, 13, (14-26)*
t AVMV t AXMX
A0 - A11
TWE
TOE
MATCH
VALID
MOTOROLA FAST SRAM
* Cache addresses used are: 14-26 for MPC2004 and MPC2007; 13-26 for MPC2005; 12-26 for MPC2006.
TAG RAM TCLR FUNCTION
CLK tSTC TCLR tSHRS DIRTYOUT tWVKH TWE tRHWX tSRST tHTC
tRSMV MATCH tRSQZ* A0 - A11 * Transition is measured plus or minus 200 mV from steady state. tRSQX VALID
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 21
ORDERING INFORMATION
(Order by Full Part Number) MPC
Motorola Memory Prefix Part Number
210x
XX
XX
Speed (66 = 66 MHz, synchronous) (15 = 15 ns asynchronous) Package (SG = Gold Pad SIMM) MPC2104 = 256KB, synchronous MPC2105 = 512KB, synchronous MPC2106 = 1MB, synchronous MPC2107 = 256KB, asynchronous
Full Part Numbers -- MPC2104SG66 MPC2105SG66 MPC2106SG66 MPC2107SG15
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MPC2104*MPC2105*MPC2106*MPC2107 22
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
MPC2104*MPC2105*MPC2106*MPC2107 23
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MPC2104*MPC2105*MPC2106*MPC2107 24
*MPC2104/D*
MOTOROLA FAST SRAM MPC2104/D

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